An analysis of accelerator coupling in heterogeneous architectures
An analysis of accelerator coupling in heterogeneous architectures
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异构架构中加速器耦合分析
DOI：
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发表时间：
2015
期刊：
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通讯作者：
L. Carloni
中科院分区：
文献类型：
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作者：
E. G. Cota;Paolo Mantovani;G. D. Guglielmo;L. Carloni
关于加速器的现有研究强调了它们可以提供的性能和能效改进，很少关注加速器调用和与其他片上组件（例如内核，缓存）的交互等实际问题。在本文中，我们提出了一个定量的研究，认为这些方面的实现7个高吞吐量的加速器以下三种设计模型：紧耦合的CPU后面，松散的核心耦合与直接内存访问（DMA）的LLC，和松散的核心耦合与DMA到DRAM。我们的研究的一个突出的结论是，非平凡大小的工作集最好由松散耦合的加速器，集成私人内存块量身定制，以满足他们的需求。
Existing research on accelerators has emphasized the performance and energy efficiency improvements they can provide, devoting little attention to practical issues such as accelerator invocation and interaction with other on-chip components (e.g. cores, caches). In this paper we present a quantitative study that considers these aspects by implementing seven high-throughput accelerators following three design models: tight coupling behind a CPU, loose out-of-core coupling with Direct Memory Access (DMA) to the LLC, and loose out-of-core coupling with DMA to DRAM. A salient conclusion of our study is that working sets of non-trivial size are best served by loosely-coupled accelerators that integrate private memory blocks tailored to their needs.