A simple model for the overlap capacitance of a VLSI MOS device
A simple model for the overlap capacitance of a VLSI MOS device
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DOI：
10.1109/t-ed.1982.21044
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发表时间：
1982-12
影响因子：
3.1
通讯作者：
R. Shrivastava;K. Fitzpatrick
中科院分区：
文献类型：
--
作者：
R. Shrivastava;K. Fitzpatrick
A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.
