A Thermoelectric Energy Generator With Double Cavity Design by Single Polysilicon Layer in Standard CMOS Process
A Thermoelectric Energy Generator With Double Cavity Design by Single Polysilicon Layer in Standard CMOS Process
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标准CMOS工艺单层多晶硅双腔设计热电发生器
DOI：
10.1109/jsen.2021.3111903
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发表时间：
2021
影响因子：
4.3
通讯作者：
L. Chung
中科院分区：
文献类型：
--
作者：
S. M. Yang;L. Chung
热电能量发生器（TEG）的性能可以通过具有更高塞贝克系数的热电偶材料、具有更好热隔离的热电偶配置以及具有有效电绝缘的薄膜层沉积/蚀刻来改善。为了获得更好的能量收集性能，提出了一种基于台积电1P6M（1层多晶硅和6层金属）标准CMOS工艺的TEG设计。在不同的掺杂率下，单一多晶硅层的面内热电偶具有更高的塞贝克效应。TEG配置采用双腔设计，可密封上下热电偶，以实现更好的热绝缘，并且沉积层采用无掩模设计，以实现更好的电绝缘。对一块5 × 5 × 5 × mm2 TEG芯片的测试结果表明，该芯片具有较高的热电转换率、较好的热绝缘性和电绝缘性<inline-formula><tex-math notation="LaTeX"></tex-math></inline-formula><sup></sup>电压因数15.604V/cm2K和功率因数0.105 μ W/cm2K2，分别比双多晶硅CMOS工艺的5.40和2.34倍。<sup></sup><inline-formula><tex-math notation="LaTeX"></tex-math></inline-formula><sup></sup><sup></sup><inline-formula><tex-math notation="LaTeX"></tex-math></inline-formula><inline-formula><tex-math notation="LaTeX"></tex-math></inline-formula>此设计、实作与实验，在半导体代工厂所有CMOS制程的TEG中，均取得最佳效能。
The performance of a thermoelectric energy generator (TEG) can be improved by having thermocouple materials with higher Seebeck coefficient, thermocouple configuration with better thermal isolation, and thin-film layer deposition/etching with effective electrical insulation. A TEG design by the 1P6M (1 polysilicon layer and 6 metal layers) standard CMOS process in semiconductor foundry service (TSMC) is proposed in this work to achieve better energy harvesting performance. The in-plane thermocouple has higher Seebeck effect by the single polysilicon layer at different doping rates. The TEG configuration is with double cavity design to seal the thermocouples above-and-below for better thermal isolation, and the deposition layers are in mask-less design for better electrical insulation. Measurement results of a <inline-formula> <tex-math notation="LaTeX">$5\times5$ </tex-math></inline-formula> mm<sup>2</sup> TEG chip show that higher thermoelectric conversion, better thermal isolation and electrical insulation can be realized. The voltage factor 15.604 V/cm<sup>2</sup>K and power factor <inline-formula> <tex-math notation="LaTeX">$0.105~\mu \text{W}$ </tex-math></inline-formula>/cm<sup>2</sup>K<sup>2</sup> are about <inline-formula> <tex-math notation="LaTeX">$5.40\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$2.34\times $ </tex-math></inline-formula>, respectively, of those of the previous work by the CMOS process with two polysilicon layers. This design, implementation, and experiment have achieved the best performance in all TEGs by CMOS process in semiconductor foundry.