SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications
SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications
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SAM：用于容错应用的基于分段的近似乘数
DOI：
10.1109/iscas51556.2021.9401266
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
D. Banerjee
中科院分区：
文献类型：
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作者：
Divy Pandey;Saurabh Singh;Vishesh Mishra;Sagar Satapathy;D. Banerjee
近年来，近似计算在能够容忍部分不准确结果的应用中得到了重要应用。这种容忍度可被利用来设计更简单的硬件，以获得面积和能耗方面的优势。在这项工作中，我们提出了一种通过基于分段的近似乘法器（SAM）来实现两个无符号二进制数相乘的新技术。所提出的设计将部分积矩阵（PPM）的大小从n×(2n - 1)阶降低到4×2n阶的简化部分积矩阵（R - PPM）。此外，它还省去了部分积压缩和重新排列所需的额外硬件。在此项工作中，我们还提出了μ - SAM，它是我们基本设计的优化版本。μ - SAM进一步最小化了基本设计的芯片面积和功耗。与传统的华莱士树乘法器[1]相比，基本设计的芯片面积消耗减少了32.43%，并且与其他现有的先进设计（如TOSAM[2]、LETAM[3]和DQ4:2C4[4]）相比，其结果准确率提高了89.1%。
In recent times, approximate computing has found significant use in applications that can tolerate partially inaccurate results. This tolerance can be exploited to design simpler hardware aimed at getting area and energy benefits. In this work, we propose a novel technique to multiply two unsigned binary numbers through a Segmentation based Approximate Multiplier (SAM). The proposed design reduces the size of the Partial Products Matrix (PPM) in the order of n × (2n — 1) to a Reduced Partial Product Matrix (R-PPM) of the order 4 × 2n. Additionally, it also eliminates the extra hardware required for compression and rearrangement of partial products. μ-SAM, an optimized version of our basic design is also proposed along with this work. μ-SAM further minimizes the on-chip area and power consumption of the basic design. The basic design consumes 32.43% lesser on-chip area when compared to the conventional Wallace tree multiplier [1] and produces results that are 89.1% more accurate when compared to other existing state-of-the-art designs such as TOSAM [2], LETAM [3], and DQ4:2C4 [4].