CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing
CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing
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CryoCore：用于低温计算的快速而密集的处理器架构
DOI：
10.1109/isca45697.2020.00037
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发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Jangwoo Kim
中科院分区：
文献类型：
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作者：
Ilkwon Byun;Dongmoon Min;Gyu;Seongmin Na;Jangwoo Kim
低温计算可以通过显着降低设备在低温下的泄漏功率和线电阻来实现高性能和功效。低温计算的最新进展集中在开发低温优化缓存和内存设备，以克服内存容量、延迟和电源墙。然而，尽管低温优化核心架构在性能、功耗和面积效率方面具有巨大潜力，但很少有研究来开发它。一旦低温优化核心可用，它也将充分利用低温优化缓存和存储设备，从而形成低温优化计算机。在本文中，我们首先开发了CryoCore-Model（CC-Modet），这是一个低温处理器建模框架，可以准确估计运行在77K的处理器模型的最大时钟频率。接下来，在建模工具的驱动下，我们设计了 CryoCore，这是一种 77K 优化核心微架构，可最大限度地提高核心性能和面积效率，同时最大限度地降低冷却成本。 CryoCore 的关键思想是构建一个内核，以减少不利于冷却的微架构单元的尺寸和数量，并最大限度地发挥 77K 电压和频率缩放的潜力。最后，我们提出了两种尺寸减半但电压缩放不同的 CryoCore 设计，旨在实现最大性能或功效。通过传统设计和集成低温存储器的设计，我们的高性能 CryoCore 设计在相同的功耗预算下实现了 41% 的单线程性能提高，在相同芯片面积的情况下实现了 2 倍的多线程性能提高。我们的低功耗 CryoCore 设计可在不牺牲单线程性能的情况下降低 38% 的功耗。
Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances towards cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture despite its high potentials in performance, power, and area efficiency. Once a cryogenic-optimal core becomes available, it will also take full advantage of the cryogenic-optimal cache and memory devices, which leads to a cryogenic-optimal computer.In this paper, we first develop CryoCore-Model (CC-Modet), a cryogenic processor modeling framework which can accurately estimate the maximum clock frequency of processor models running at 77K. Next, driven by the modeling tool, we design CryoCore, a 77K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The key idea of CryoCore is to architect a core in a way to reduce the size and number of cooling-unfriendly microarchitecture units and maximize the potential of a voltage and frequency scaling at 77K. Finally, we propose two halfsized, but differently voltage-scaled CryoCore designs aiming for either the maximum performance or power efficiency. With both conventional and our design integrated with cryogenic memories, our high-performance CryoCore design achieves 41% higher single-thread performance for the same power budget and 2x higher multi-thread performance for the same die area. Our lowpower CryoCore design reduces the power cost by 38% without sacrificing the single-thread performance.