On the design of low-power cache memories for homogeneous multi-core processors
On the design of low-power cache memories for homogeneous multi-core processors
复制标题
同构多核处理器低功耗高速缓冲存储器的设计
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
F. Sibai
中科院分区：
文献类型：
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作者：
A. Asaduzzaman;M. Rani;F. Sibai
我们调查的影响1级缓存（CL 1）参数，2级缓存（CL 2）参数，和缓存组织的功耗和性能的多核系统。我们模拟了两个4核架构-都使用私有CL 1，但一个使用共享CL 2，另一个使用私有CL 2。MPEG4、H.264、矩阵求逆和DFT工作负载的仿真结果表明，使用优化的CL 1和CL 2，可以分别将总功耗和每个任务的平均延迟降低高达42%和48%。总功耗和每个任务的平均延迟显着依赖于应用程序，包括代码大小和位置。
We investigate the impact of level-1 cache (CL1) parameters, level-2 cache (CL2) parameters, and cache organizations on the power consumption and performance of multi-core systems. We simulate two 4-core architectures - both with private CL1s, but one with shared CL2 and the other one with private CL2s. Simulation results with MPEG4, H.264, matrix inversion, and DFT workloads show that reductions in total power consumption and mean delay per task of up to 42% and 48%, respectively, are possible with optimized CL1s and CL2s. Total power consumption and the mean delay per task depend significantly on the applications including the code size and locality.