Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement
复制标题
使用变化感知布局提高 FPGA 中基于 PUF 的密钥生成的效率
DOI：
10.1109/fpl.2016.7577307
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
Daniel E. Holcomb
中科院分区：
文献类型：
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作者：
Shrikant Vyas;Naveen Kumar Dumpala;R. Tessier;Daniel E. Holcomb
可重新配置的系统通常需要秘密密钥来加密和解密数据。需要高安全性的应用通常基于物理不可克隆功能（PUF）生成密钥，物理不可克隆功能（PUF）是使用随机制造变化来产生每个设备唯一的密钥的电路。基于PUF的密钥的安全性以高硬件成本为代价。由于需要纠错以从有噪声的PUF中提取可靠的密钥，因此n位密钥的总成本远远超过产生n位PUF输出的成本。在这项工作中，我们提出了变化感知的FPGA内PUF布局，以减少FPGA上基于PUF的密钥的面积成本。我们表明，根据每个芯片实例的随机变化放置PUF实例降低了PUF的误码率，从而大大降低了密钥生成的整体成本。所提出的变化感知布局方法适用于任何基于PUF的系统中实现的可重构逻辑。我们在Xilinx Zynq-7000可编程SoC上演示了我们的方法，该SoC使用FPGA特定的PUF，基于BCH码进行码偏移纠错。我们量化我们的方法的有效性，通过比较相同系统的实施成本时，使用的默认方法的变化不可知的位置和我们提出的变化感知的位置。结果表明，我们的方法减少了约50%的PUF和纠错电路所需的面积，同时实现等效的可靠性。
Reconfigurable systems often require secret keys to encrypt and decrypt data. Applications requiring high security commonly generate keys based on physical unclonable functions (PUFs), circuits which use random manufacturing variations to produce secret keys that are unique to each device. The security of PUF-based keys comes at a high hardware cost. Due to the need for error correction to extract reliable keys from noisy PUFs, the total cost of an n-bit key far exceeds just the cost of producing n bits of PUF output. In this work, we propose variation-aware intra-FPGA PUF placement to reduce the area cost of PUF-based keys on FPGAs. We show that placing PUF instances according to the random variations of each chip instance reduces the bit error rate of the PUFs and consequently greatly reduces the overall cost of key generation. The proposed variation-aware placement approach is applicable to any PUF-based system implemented in reconfigurable logic. We demonstrate our approach on a Xilinx Zynq-7000 Programmable SoC using FPGA-specific PUFs with code-offset error correction based on BCH codes. We quantify the effectiveness of our approach by comparing the implementation costs of the same system when using the default approach of variation-agnostic placement and our proposed variation-aware placement. It is shown that our approach reduces the area required for PUF and error-correction circuitry by about 50% while achieving equivalent reliability.