Guarded dual rail logic for soft error tolerant standard cell library
Guarded dual rail logic for soft error tolerant standard cell library
复制标题
用于软容错标准单元库的受保护双轨逻辑
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
Joycee Mekie
中科院分区：
文献类型：
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作者：
Raminder Kaur;Neelam Surana;Joycee Mekie
本文提出了一种将互补双轨逻辑和保护门相结合的新技术，称为保护双轨逻辑（GDRL），以减轻单粒子效应。TCAD模拟验证了65 nm工艺中保护栅的SET滤波特性，LET值达到100 MeV-cm ~ 2/mg。为了比较建议GDRL设计与TMR，我们使用了ISCAS基准电路。与TMR实现相比，使用所提出的技术设计的电路消耗的功率减少了57%。
A novel technique that combines complementary dual rail logic and guard gate, referred to as Guarded Dual Rail Logic (GDRL) to mitigate single event effects is proposed in this paper. TCAD simulations have been done to validate the SET filtering properties of guard gate in 65nm technology for LET values up to 100MeV-cm2/mg. To compare proposed GDRL design with TMR, we have used ISCAS benchmark circuits. Circuits designed with proposed technique consume ∼57% less power compared to their TMR implementation.