Morrigan: A Composite Instruction TLB Prefetcher
Morrigan: A Composite Instruction TLB Prefetcher
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DOI：
10.1145/3466752.3480049
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发表时间：
2021-10
期刊：
影响因子：
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通讯作者：
Georgios Vavouliotis;Lluc Alvarez;Boris Grot;Daniel A. Jiménez;Marc Casas
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作者：
Georgios Vavouliotis;Lluc Alvarez;Boris Grot;Daniel A. Jiménez;Marc Casas
减少地址转换开销的努力通常以数据访问为目标，因为它们构成了桌面和HPC应用中第二级TLB（STLB）未命中的绝大部分。由于历史上指令占用空间较小，指令访问的地址转换成本相对被忽略。然而，由于深度软件栈，最先进的数据中心和服务器应用程序具有大量指令占用空间，导致指令访问的高STLB未命中率。本文证明了指令地址转换是服务器工作负载中的性能瓶颈。作为回应，我们提出Morrigan，一个微架构的指令STLB预取器，其设计是基于新的见解，关于指令STLB失误。在Morrigan的核心，有一个基于表的马尔可夫预取器的集合，它从指令STLB未命中流中构建和存储可变长度的马尔可夫链。Morrigan还采用了顺序预取器和利用页表局部性来最大化未命中覆盖的方案。这项工作的一个重要贡献是，在选择替换候选人时，访问频率比访问新近度更重要。基于这一见解，Morrigan引入了一种新的替换策略，该策略使用频率堆栈来识别马尔可夫预取器中的受害者，同时适应相变行为。在一组45个工业服务器工作负载上，Morrigan消除了由指令STLB未命中触发的按需页遍历中69%的内存引用，并将几何平均性能提高了7.6%。
The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address translation cost of instruction accesses has been relatively neglected due to historically small instruction footprints. However, state-of-the-art datacenter and server applications feature massive instruction footprints owing to deep software stacks, resulting in high STLB miss rates for instruction accesses. This paper demonstrates that instruction address translation is a performance bottleneck in server workloads. In response, we propose Morrigan, a microarchitectural instruction STLB prefetcher whose design is based on new insights regarding instruction STLB misses. At the core of Morrigan there is an ensemble of table-based Markov prefetchers that build and store variable length Markov chains out of the instruction STLB miss stream. Morrigan further employs a sequential prefetcher and a scheme that exploits page table locality to maximize miss coverage. An important contribution of the work is showing that access frequency is more important than access recency when choosing replacement candidates. Based on this insight, Morrigan introduces a new replacement policy that identifies victims in the Markov prefetchers using a frequency stack while adapting to phase-change behavior. On a set of 45 industrial server workloads, Morrigan eliminates 69% of the memory references in demand page walks triggered by instruction STLB misses and improves geometric mean performance by 7.6%.