Low-cost router microarchitecture for on-chip networks
Low-cost router microarchitecture for on-chip networks
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DOI：
10.1145/1669112.1669145
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发表时间：
2009-12
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通讯作者：
John Kim
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文献类型：
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作者：
John Kim
片上网络对于未来多核心处理器的缩放至关重要。芯片网络面临的挑战是降低成本，包括功耗和面积，同时提供高延迟和高带宽等高性能。尽管片上网络的大量研究重点是提高片网络的性能，但它们通常依靠芯片外网络采用的路由器微体系结构。结果，由于设计复杂性，片上网络体系结构将无法正确扩展。在本文中，我们提出了一个低成本的芯片网络路由器微构造，该结构与通常假定的基线路由器微体系结构不同。我们通过分区横梁来降低片上网络的成本，在飞行中优先考虑数据包以简化仲裁，并减少缓冲区的数量。我们表明，通过引入中间缓冲液以将X和Y尺寸的路由解次，可以使用所提出的低成本路由器微体系结构来实现高性能。通过删除基线路由器微体系结构的复杂性，低成本路由器微构造也可以接近芯片网络中理想的延迟。但是，优先的开关仲裁简化了路由器，但为某些节点创建饥饿。我们展示了如何将延迟利率信用归还上游返回的利率信用量可以用于实施分布式饥饿的回避机制以提供公平。我们的评估表明，与实现相似吞吐量的基线路由器的微构造相比，拟议的低成本路由器可以将面积降低37％，功率消耗量可以降低45％。
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while providing high performance such as low latency and high bandwidth. Although much research in on-chip network have focused on improving the performance of on-chip networks, they have often relied on a router microarchitecture adopted from off-chip networks. As a result, the on-chip network architecture will not scale properly because of design complexity. In this paper, we propose a low-cost, on-chip network router microarchitecture which is different from the commonly assumed baseline router microarchitecture. We reduce the cost of on-chip networks by partitioning the crossbar, prioritizing packets in flight to simplify arbitration, and reducing the amount of buffers. We show that by introducing intermediate buffers to decouple the routing in the x and the y dimensions, high performance can be achieved with the proposed, low-cost router microarchitecture. By removing the complexity of a baseline router microarchitecture, the low-cost router microarchitecture can also approach the ideal latency in on-chip networks. However, the prioritized switch arbitration simplifies the router but creates starvation for some nodes. We show how delaying the rate credits are returned upstream can be used to implement a distributed, starvation avoidance mechanism to provide fairness. Our evaluations show that the proposed low-cost router can reduce the area by 37% and the power consumption by 45% compared with a baseline router microarchitecture that achieves a similar throughput.