A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
复制标题
时钟门控设计的可重配置时钟极性分配流程
DOI：
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发表时间：
2012
影响因子：
2.8
通讯作者：
B. Taskin
中科院分区：
文献类型：
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作者：
Jianchao Lu;Y. Teng;B. Taskin
本文提出了一种允许硅后可重新配置的时钟极性分配流程。所提出的方法在时钟树的一层插入异或门以促进极性分配。可以针对不同的时钟门控模式（睡眠模式、繁忙模式等）重新配置异或门的极性，从而可以实现峰值电流的特定于模式的降低。实验结果表明，通过为时钟树接收级的异或门分配极性，可以将时钟树上最坏情况下的峰值电流降低 33.3%。通过根据时钟门控信息重新配置极性分配，可以将最坏情况下的峰值电流额外降低 12.8%。所提出的流程使面积增加了 7.1%，但总功耗减少了 23.8%，全局时滞增加（由于极性分配）从 19.3 ps 减少到 8.8 ps。还研究了在非汇聚节点插入异或门，以进一步减少全局偏斜增加和面积开销。
This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to xor gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of xor gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.