Tolerating process variations in high-level synthesis using transparent latches
Tolerating process variations in high-level synthesis using transparent latches
复制标题
使用透明锁存器容忍高级综合中的工艺变化
DOI：
10.1109/aspdac.2009.4796444
复制
发表时间：
2009
期刊：
影响因子：
--
通讯作者：
Yuan Xie
中科院分区：
文献类型：
--
作者：
Yibo Chen;Yuan Xie
在行为综合级别考虑工艺可变性是必要的，因为这会使功能单元的某些实例变慢，而使其他实例变得更快，从而导致控制步骤不平衡，并降低电路的可达到频率。为了解决这一问题，本文提出了一种用透明锁存器取代边沿触发器的方法，以利用锁存器额外的传递时间松弛和容忍延迟变化的能力。在本文中，我们首先定义了高级综合中的时序良率，然后介绍了如何用锁存器代替触发器来提高时序良率和减轻工艺变化的影响。然后，我们讨论了替换的好处和开销，并提出了高级综合设计流程中锁存器替换的优化框架。实验结果表明，与传统的基于触发器的设计相比，基于锁存器的设计平均可以提高27%的时序良率。
Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced control steps and reducing the attainable frequency of the circuit. To tackle this problem, this paper proposes a methodology to replace the edge-trigged flip-flops by transparent latches, to exploit latches' extra ability of passing time slacks and tolerating delay variations. In the paper we first define the timing yield in high-level synthesis, and then present how to replace flip-flops with latches to improve timing yield and mitigate the impact of process variations. We then discuss the benefits and overheads for the replacement, and propose an optimization framework for latch replacement in high-level synthesis design flow. Experimental results show that the latch-based design can achieve an average of 27% improvement of timing yield compared with traditional flip-flop based design.