New three-dimensional integration technology using self-assembly technique

New three-dimensional integration technology using self-assembly technique
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DOI：
10.1109/iedm.2005.1609347
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发表时间：
2005-12
期刊：
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
影响因子：
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通讯作者：
T. Fukushima;Yusuke Yamada;H. Kikuchi;M. Koyanagi
T. Fukushima;Yusuke Yamada;H. Kikuchi;M. Koyanagi
中科院分区：
其他
文献类型：
--
作者：
T. Fukushima;Yusuke Yamada;H. Kikuchi;M. Koyanagi

文献摘要

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为了实现最终的超级芯片集成，我们开发了一种三维集成技术，称为超级智能堆栈技术，采用自组装技术。采用自组装技术，实现了1 μ m以内的芯片对准精度。我们首次展示了使用超智能堆栈（SSS）技术成功制造了具有十层存储层的3D SRAM测试芯片
To achieve ultimate super chip integration, we have developed a three-dimensional integration technology called super-smart-stack technology using a self-assembly technique. The chip alignment accuracy of within 1mum is obtained by the self-assembly technique. We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology