Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates
Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates
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DOI：
10.1109/ted.2013.2272324
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发表时间：
2013-07
影响因子：
3.1
通讯作者：
Karl‐Magnus Persson;M. Berg;M. Borg;Jun Wu;Sofia Johansson;J. Svensson;K. Jansson;E. Lind;L. Wernersson
中科院分区：
文献类型：
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作者：
Karl‐Magnus Persson;M. Berg;M. Borg;Jun Wu;Sofia Johansson;J. Svensson;K. Jansson;E. Lind;L. Wernersson
本文介绍了LG=200 nm、Al 2 O3/HfO 2高κ介质的垂直InAs纳米线（NW）MOSFET的直流和射频特性以及建模。在VDS=0.5 V下的测试结果表明，采用Si衬底上的垂直InAs纳米线，可以实现高导通电阻（gm=1.37 mS/μm）、高驱动电流（IDS=1.34 mA/μm）和低导通电阻（罗恩=287 Ωμm）。通过测量1/f噪声，确定了栅面积归一化栅电压噪声谱密度SVG·LG·WG，与仅由HfO 2组成的高κ膜的类似器件相比降低了一个数量级。此外，与虚源模型，我们能够确定的内在传输特性。这些器件（LG=200 nm）显示出高注入速度（vinj=1.7×107 cm/s），阵列FET的性能下降主要是由于串联电阻的增加。
This paper presents dc and RF characterization as well as modeling of vertical InAs nanowire (NW) MOSFETs with LG=200 nm and Al2O3/HfO2 high-κ dielectric. Measurements at VDS=0.5 V show that high transconductance (gm=1.37 mS/μm), high drive current (IDS=1.34 mA/μm), and low ON-resistance (RON=287 Ωμm) can be realized using vertical InAs NWs on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, SVG·LG·WG, is determined to be lowered by one order of magnitude compared with similar devices with a high-κ film consisting of HfO2 only. In addition, with a virtual source model we are able to determine the intrinsic transport properties. These devices (LG=200 nm) show a high injection velocity (vinj=1.7×107 cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.