Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
复制标题
65 nm CMOS逻辑门最低工作电压的决定因素研究
DOI：
10.1109/islped.2011.5993598
复制
发表时间：
2011
期刊：
影响因子：
--
通讯作者：
T. Sakurai
中科院分区：
文献类型：
--
作者：
Tadashi Yasufuku;S. Iida;H. Fuketa;K. Hirairi;M. Nomura;M. Takamiya;T. Sakurai
通过对65 nm CMOS中逻辑门链的测量，研究了影响CMOS门最小工作电压(V<；Inf>；DDmin<；/Inf>；)的决定因素。由系统成分(V<；inf>；DDmin(Ys)/inf&>)和随机变异成分(V<；inf>；DDmin(RAND)<；/inf&>)组成。当逻辑门的逻辑阈值电压等于一半电源电压(V<；inf>；DD<；/inf>；)时，V<；inf>；DDmin(Ys)<；/inf>；被最小化。通过调整NMOS/PMOS的栅宽来实现各逻辑门的逻辑阈值电压的调节。V<；inf>；DDmin(RAND)<；/inf>；通过减小通过增加栅极宽度或正向主体偏置实现的随机阈值变化来最小化。此外，还首次测量了V<；Inf>；DDmin<；/Inf>；的温度依赖关系。V<；inf>；DDmin<；/inf>；的最差拐角分析的温度应根据逻辑电路的门数而改变。
Determinant factors of the minimum operating voltage (V<inf>DDmin</inf>) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. V<inf>DDmin</inf> consists of a systematic component (V<inf>DDmin(SYS)</inf>) and a random variation component (V<inf>DDmin(RAND)</inf>). V<inf>DDmin(SYS)</inf> is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (V<inf>DD</inf>). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. V<inf>DDmin(RAND)</inf> is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of V<inf>DDmin</inf> is measured for the first time. The temperature for the worst corner analysis for V<inf>DDmin</inf> should be changed depending on the number of gate counts of logic circuits.