Layout Driven Data Communication Optimization for High Level Synthesis
Layout Driven Data Communication Optimization for High Level Synthesis
复制标题
用于高级综合的布局驱动数据通信优化
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
M. Sarrafzadeh
中科院分区：
文献类型：
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作者：
R. Kastner;Wenrui Gong;X. Hao;F. Brewer;A. Kaplan;P. Brisk;M. Sarrafzadeh
高级综合变换在形成最终电路的特性方面起着重要作用。然而，大多数优化是在没有太多最终电路布局知识的情况下执行的。在本文中，我们提出了一个物理感知的设计流程映射高层次的应用规范，一个可合成的寄存器传输级硬件描述。我们研究的问题，优化的应用程序规范中的变量的数据通信。我们的算法使用的布局信息，指导优化。我们开发了一个简单而有效的增量式布局规划器来处理由数据通信优化引起的扰动。我们表明，所提出的技术可以减少最终设计的线长，同时保持与初始布图规划相同面积的法律的布图规划
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan