Ultra high density logic designs using transistor-level monolithic 3D integration
Ultra high density logic designs using transistor-level monolithic 3D integration
复制标题
使用晶体管级单片 3D 集成的超高密度逻辑设计
DOI：
--
复制
发表时间：
2012
期刊：
影响因子：
--
通讯作者：
S. Lim
中科院分区：
文献类型：
--
作者：
Young;P. Morrow;S. Lim
单片3D技术的最新创新实现了比当今基于硅通孔（TSV）的技术更高密度的垂直连接。在本文中，我们调查的好处和挑战的单片3D集成技术的超高密度逻辑设计。基于我们的布局实验，我们比较重要的设计指标，如面积，线长，时序，功耗单片3D设计与传统的2D设计。我们还探索单片3D IC的各种互连选项，以提高设计密度和质量。根据单片3D IC的互连设置和基准电路特性，我们观察到，我们的双层单片3D设计与2D设计相比，可减少多达40%的占用空间，缩短27.7%的线长，加快39.7%的运行速度，并降低9.7%的功耗。
Recent innovations in monolithic 3D technology enable much higher-density vertical connections than today's through-silicon-via (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout experiments, we compare important design metrics such as area, wirelength, timing, and power consumption of monolithic 3D designs with the traditional 2D designs. We also explore various interconnect options for monolithic 3D ICs that improve design density and quality. Depending on the interconnect settings of monolithic 3D ICs and the benchmark circuit characteristics, we observe that our two-tier monolithic 3D design provides up to 40% reduced footprint, 27.7% shorter wirelength, 39.7% faster operation, and 9.7% lower power consumption over the 2D counterpart.