A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device
A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device
复制标题
>100 Gbps 内联 AES-GCM 硬件引擎以及 SGX Enclave 和 FPGA 加速器设备之间受保护的 DMA 传输
DOI：
--
复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Reshma Lal
中科院分区：
文献类型：
--
作者：
Santosh K. Ghosh;L. S. Kida;S. Desai;Reshma Lal
本文提出了一种保护DMA数据传输的方法，该方法可用于将计算卸载到加速器上。该建议最大限度地减少了硬件平台以及应用程序和软件堆栈的变化。本文描述了端到端方案，以保护在SGX enclave内运行的应用程序与针对带宽和延迟进行优化的FPGA加速器之间的通信，并详细介绍了具有高带宽和低延迟的AES-GCM硬件引擎的实现。
This paper proposes a method to protect DMA data transfer that can be used to offload computation to an accelerator. The proposal minimizes changes in the hardware platform and to the application and SW stack. The paper describes the end-to-end scheme to protect communication between an application running inside a SGX enclave and a FPGA accelerator optimized for bandwidth and latency and details the implementation of AES-GCM hardware engines with high bandwidth and low latency.