An event-driven massively parallel fine-grained processor array
An event-driven massively parallel fine-grained processor array
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DOI：
10.1109/iscas.2015.7168891
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发表时间：
2015-05
期刊：
影响因子：
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通讯作者：
Declan Walsh;P. Dudek
中科院分区：
文献类型：
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作者：
Declan Walsh;P. Dudek
提出了一种基于事件驱动的多核并行处理器阵列设计。使用相对简单的8位处理核心和2D Mesh网络拓扑，该体系结构侧重于减少单个处理器核心的面积占用。大量这样的处理器核心可以在单个集成芯片上实现，以创建能够提供强大处理性能的MIMD体系结构。每个处理器核心都是一个事件驱动的处理器，当没有数据在本地改变时，它可以进入空闲模式。在1,875μm×1,875μm的CMOS65 nm工艺中实现了一个8×8的原型处理器阵列，该处理器阵列能够在80 MHz下运行5.12GOPS，平均功耗为75.4 mW。
A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a single processor core. A large number of these processor cores can be implemented on a single integrated chip to create a MIMD architecture capable of providing a powerful processing performance. Each processor core is an event-driven processor which can enter an idle mode when no data is changing locally. An 8 × 8 prototype processor array is implemented in a 65 nm CMOS process in 1,875 μm × 1,875 μm. This processor array is capable of performing 5.12 GOPS operating at 80 MHz with an average power consumption of 75.4 mW.