A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS
复制标题
40nm CMOS数字电路的温度和工艺角不敏感设计方法
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
F. Gerfers
中科院分区：
文献类型：
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作者：
Marcel Runge;Sebastian Linnhoff;F. Gerfers
本文提出了一种数字设计方法，可以在40 nm的CMOS中实现跨越温度和工艺拐角的恒定路径延迟。因此，大大简化了时序分析和逻辑综合。通过在零温度系数电源电压下工作，消除了温度依赖性。此外，工艺拐角自适应主体偏置补偿了工艺拐角相关的路径延迟。各种标准单元的广泛晶体管级模拟显示，温度和6个σ工艺拐角的路径延迟恒定。所有施加的主体偏置电压都在晶体管的可靠性范围内。这种方法可以实现快速的数字合成，而不需要耗时的过程和温度分析和优化。
This paper proposes a digital design method enabling a constant path delay across temperature and process corners in 40nm CMOS. Thus, timing analysis and logic synthesis is simplified significantly. The temperature dependency is eliminated by operating at the zero temperature coefficient supply voltage. Additionally, process corner adaptive body biasing compensates process corner dependent path delays. Extensive transistor level simulations for various standard cells show constant path delays across temperature and 6σ process corners. All applied body bias voltages lie within the transistor reliability. This method enables rapid digital synthesis without time consuming process and temperature analyses and optimization.