Polymorphic gate based IC watermarking techniques
Polymorphic gate based IC watermarking techniques
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DOI：
10.1109/aspdac.2018.8297288
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发表时间：
2018-01
期刊：
影响因子：
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通讯作者：
Tian Wang;Xiaohui Cui;Dunshan Yu;Omid Aramoon;Timothy Dunlap;G. Qu;Xiaole Cui
中科院分区：
文献类型：
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作者：
Tian Wang;Xiaohui Cui;Dunshan Yu;Omid Aramoon;Timothy Dunlap;G. Qu;Xiaole Cui
多态门是一种可重新配置的器件，其功能可以随着执行环境的变化而变化，例如温度、电源电压或外部控制信号。这一功能使它们成为电路水印的完美候选者。然而，多态门很难找到，因为它们没有表现出传统的结构。在这篇文章中，我们报告了四个双功能多态门，我们已经发现了使用进化的方法。利用这些门，我们提出了一种电路水印方案，它选择性地将某些标准逻辑门替换为多态门。在ISCAS和MCNC基准电路上的实验结果表明，该方案具有较低的开销。更具体地说，在嵌入30位水印序列时，面积、速度和功耗的平均开销分别为4.10%、2.08%和1.17%。当替换原电路中10%的门以嵌入300比特以上的水印时，这些开销分别增加到6.36%、4.75%和2.08%。
Polymorphic gates are reconfigurable devices whose functionality may vary in response to the change of execution environment such as temperature, supply voltage or external control signals. This feature makes them a perfect candidate for circuit watermarking. However, polymorphic gates are hard to find because they do not exhibit the traditional structure. In this paper, we report four dual-function polymorphic gates that we have discovered using an evolutionary approach. With these gates, we propose a circuit watermarking scheme that selectively replaces certain standard logic gates with the polymorphic gates. Experimental results on ISCAS and MCNC benchmark circuits demonstrate that this scheme introduces low overhead. More specifically, the average overhead in area, speed and power are 4.10%, 2.08% and 1.17% respectively when we embed 30-bit watermark sequences. These overheads increase to 6.36%, 4.75% and 2.08% respectively when 10% of the gates in the original circuits are replaced to embed watermark up to more than 300 bits.