Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
复制标题
用于可重构片上系统设计的区域高效指令集综合
DOI：
10.1145/996566.996679
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
M. Sarrafzadeh
中科院分区：
文献类型：
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作者：
P. Brisk;A. Kaplan;M. Sarrafzadeh
硅编译器通常与现场可编程门阵列（fpga）结合使用，以提供灵活性，快速原型设计和加速上市时间。许多这样的编译器产生的硬件比需要的大，因为它们不允许指令共享硬件资源。本研究提出了一种有效的启发式方法，将一组自定义指令转换为单个硬件数据路径，并在该路径上执行这些指令。我们的方法是基于寻找两个（或多个）序列的最长公共子序列和子串的经典问题。这种启发式方法比不探索资源共享的整数线性规划（ILP）方法合成的电路小85.33%。管道数据路径的平均面积减少55.41%，VLIW数据路径的平均面积减少66.92%。我们的解决方案简单有效，可以很容易地集成到现有的硅编译器中。
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these compilers produce hardware that is larger than necessary, as they do not allow instructions to share hardware resources. This study presents an efficient heuristic which transforms a set of custom instructions into a single hardware datapath on which they can execute. Our approach is based on the classic problems of finding the longest common subsequence and substring of two (or more) sequences. This heuristic produces circuits which are as much as 85.33% smaller than those synthesized by integer linear programming (ILP) approaches which do not explore resource sharing. On average, we obtained 55.41% area reduction for pipelined datapaths, and 66.92% area reduction for VLIW datapaths. Our solution is simple and effective, and can easily be integrated into an existing silicon compiler.