Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
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MPSoC 中 WIDE I/O DRAM 的保留时间测量和误码率建模
DOI：
10.7873/date.2015.0258
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
N. Wehn
中科院分区：
文献类型：
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作者：
C. Weis;Matthias Jung;Peter Ehses;C. Santos;P. Vivet;Sven Goossens;Martijn Koedam;N. Wehn
DRAM单元使用电容器作为易失性和漏泄位存储元件。没有刷新它们所花费的时间称为保留时间。众所周知，保留时间与温度成反比。在3D堆叠中，高功率密度和散热的挑战加剧，并对放置在MPSoC顶部的3D堆叠宽I/O DRAM的保留时间产生更大的影响。因此，研究宽I/O动态随机存储器的温度特性是非常重要的。据我们所知，对于堆叠的DRAM-on-Logic器件，没有基于实际测量的调查。本文首先对宽I/O动态随机存储器的保持时间和误码率随温度的变化进行了详细的测量。为了获得宽I/O DRAM芯片的正确温度分布，我们使用了一种先进的热建模工具：DOCEA AceTherMalModelerTM(ATM)。借助先进的基于现场可编程门阵列的测试系统，将宽I/O DRAM保留时间和误码率与2D-DRAM芯片(DIMM)的行为进行了比较。我们观察到数据模式依赖关系和可变保留时间(VRT)。其次，基于这些数据，我们开发并验证了SystemC-TLM2.0DRAM误码率模型。我们提出的DRAM比特错误模型使我们能够在未来的3D堆叠MPSoC中早期研究温度与保留时间之间的权衡，这些MPSoC具有广泛的I/O DRAM，在System C-TLM2.0环境中。
DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent without refreshing them is called retention time. It is well known that the retention time depends inverse exponentially on the temperature. In 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated and have a much stronger impact on the retention time of 3D-stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behaviour of WIDE I/O DRAMs. To the best of our knowledge, no investigations based on real measurements were done for stacked DRAM-on-logic devices. In this paper, we first provide detailed measurements on temperature-dependent retention time and bit error rates of WIDE I/O DRAMs. To obtain the correct temperature distribution of the WIDE-I/O DRAM die we use an advanced thermal modelling tool: the DOCEA AceThermalModelerTM (ATM). The WIDE I/O DRAM retention times and bit error rates are compared to the behaviour of 2D-DRAM chips (DIMMs) with the help of an advanced FPGA-based test system. We observed data pattern dependencies and variable retention times (VRTs). Second, based on this data, we develop and validate a SystemC-TLM2.0 DRAM bit error rate model. Our proposed DRAM bit error model enables early investigations on the temperature vs. retention time trade-off in future 3D-stacked MPSoCs with WIDE I/O DRAMs in SystemC-TLM2.0 environments.