Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
复制标题
基于 Eager Evaluation 的时序鲁棒异步电路的块级松弛
DOI：
10.1109/async.2008.25
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
S. Nowick
中科院分区：
文献类型：
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作者：
Cheoljoo Jeong;S. Nowick
随着可变性和时序关闭成为同步CAD流程中的关键挑战，一个有吸引力的替代方案是使用健壮的异步电路，它可以优雅地适应时序差异。在这种方法中，初始布尔网表中的每个门通常由一个健壮的双轨异步模板代替。然而，这些电路通常具有显著的面积和延迟开销。最近提出了一种门级放松方法：用执行渴望评估的异步模板替换选定的简单门，而不影响电路的整体时序鲁棒性。在本文中，该方法已被显著扩展到块级松弛：处理任意复杂的多输出块。对于这些电路，可适用的优化范围比门级方法大得多。实现了一种块级松弛算法，并在几种高速算术电路（Brent-Kung加法器和Kogge-Stone加法器、组合乘法器）上进行了实验。平均而言，可以放松38.4%的块（48.4%的最佳情况），关键路径的面积改善27.2%（49.7%的最佳情况），延迟改善13.1%（25.5%的最佳情况），同时仍然保持电路的整体时序鲁棒性。
As variability and timing closure become critical challenges in synchronous CAD flows, one attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. In this approach, each gate in an initial Boolean netlist is typically replaced by a robust dual-rail asynchronous template. However, these circuits typically have significant area and latency overhead. A gate-level relaxation approach has recently been proposed: replacing selected simple gates by asynchronous templates performing eager evaluation, without affecting the circuit's overall timing robustness. In this paper, the approach has been significantly extended to block-level relaxation: handling arbitrarily complex multi-output blocks. For these circuits, a much wider range of optimizations is applicable than in the gate-level approach. A block-level relaxation algorithm is implemented, and experiments performed on several high-speed arithmetic circuits (Brent-Kung and Kogge-Stone adders, combinational multipliers). On average, 38.4\% of the blocks could be relaxed (48.4\% best-case),with area improvement of 27.2% (49.7% best-case)and delay improvement of 13.1% (25.5% best-case) for the critical path,while still preserving the circuit's overall timing robustness.