A novel architecture of the 3D stacked MRAM L2 cache for CMPs
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
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DOI：
10.1109/hpca.2009.4798259
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发表时间：
2009-03
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影响因子：
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通讯作者：
Guangyu Sun;Xiangyu Dong;Yuan Xie;Jian Li;Yiran Chen
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文献类型：
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作者：
Guangyu Sun;Xiangyu Dong;Yuan Xie;Jian Li;Yiran Chen
磁随机访问记忆（MRAM）是一种有前途的内存技术，它具有快速读取访问，高密度和不挥发性的方法。使用3D异质整合，在常规芯片多处理器（CMP）上堆放MRAM变得可行且具有成本效益。但是，MRAM的一个缺点是它的文字延迟和高写入能量。在本文中，我们首先直接在CMP上堆叠基于L2的L2缓存，并将其与SRAM对应物进行比较。我们观察到，直接的MRAM堆叠可能会损害上述长写入延迟和高写入能量，因此芯片性能会损害芯片性能。为了解决这个问题，我们提出了两种架构技术：读取式写入缓冲液和SRAM-MRAM混合L2缓存。模拟结果表明，与常规的SRAM L2高速缓存相比，我们优化的MRAM L2高速缓存提高了4.91％，并将功率降低了73.5％。
Magnetic random access memory (MRAM) is a promising memory technology, which has fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack MRAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of MRAM is its long write latency and its high write energy. In this paper, we first stackMRAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. We observe that the direct MRAM stacking might harm the chip performance due to the aforementioned long write latency and high write energy. To solve this problem, we then propose two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache. The simulation result shows that our optimized MRAM L2 cache improves performance by 4.91% and reduces power by 73.5%compared to the conventional SRAM L2 cache with the similar area.