Reconciling the IC test and security dichotomy
Reconciling the IC test and security dichotomy
复制标题
协调 IC 测试和安全二分法
DOI：
10.1109/ets.2013.6569368
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
Y. Makris
中科院分区：
文献类型：
--
作者：
O. Sinanoglu;Naghmeh Karimi;Jeyavijayan Rajendran;R. Karri;Yier Jin;K. Huang;Y. Makris
许多设计公司负担不起拥有和收购昂贵的代工厂，因此，去无晶圆厂和外包他们的设计制造到代工厂，这是潜在的不信任。集成电路（IC）设计流程的全球化带来了安全漏洞。如果设计是在不受（无晶圆厂）设计公司直接控制的代工厂中制造的，则逆向工程、恶意电路修改和知识产权（IP）盗版都是可能的。在本教程中，我们将通过与VLSI测试的连接来详细说明这些和类似的硬件安全威胁。我们涵盖了可信设计技术，如逻辑加密、老化加速攻击和有助于识别木马艾德和假冒IC的统计方法。
Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.