A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing
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DOI：
10.1109/candar.2017.46
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发表时间：
2017-11
期刊：
影响因子：
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通讯作者：
Renyuan Zhang;Takashi Nakada;Y. Nakashima
中科院分区：
文献类型：
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作者：
Renyuan Zhang;Takashi Nakada;Y. Nakashima
模拟计算电路在近似计算应用中具有晶体管和互连少、速度快、功耗低的优点，但存在可编程性差的问题。这项工作探索了一种可编程模拟电路的架构，以可接受的精度计算任意函数。采用支持向量回归（SVR）算法对任意特定函数进行仿真。设计了一组模拟电路来实现回归网络，其中相关参数是动态可编程的，以指定目标函数。提出了一种有效的支持向量回归算法方案，以缩小回归网络和电路实现的规模。通过这种方式，仅用600个晶体管就可以实时计算两个操作数之间的任意函数。该演示处理器称为模拟计算单元（ACU），采用标准CMOS技术进行设计和模拟，以进行概念验证。电路仿真结果表明，所提出的ACU能够实时计算所有目标函数，误差小于4.3%。所提出的ACU在速度、功能和硬件效率方面的性能都优于基本的四位数字算术逻辑单元（ALU）。显然，所提出的ACU的计算能力要高于仅处理几个基本算术和逻辑功能的简单的4位ALU。对于任意四位计算，ACU的晶体管数量仅为传统现场可编程门阵列（FPGA）最小估计的4.9%。此外，采用我们提出的功率门控方案消除了所设计的ACU的静态功率。
The analog calculating circuits perform with benefits on fewer transistors and interconnections, high speed, and low power for the approximate computing applications, but suffer from the poor programmability. This work explores an architecture of programmable analog circuitry to calculate arbitrary functions with acceptable accuracy. The support vector regression (SVR) algorithm is employed to emulate any specific functions. A set of analog circuits are designed for implementing the regression network, in which the relevant parameters are dynamically programmable to specify the target function. An efficient scheme of SVR algorithm is proposed to shrink the scale of regression network and circuit implementations. In this manner, the arbitrary functions between two operands can be computed in real-time with only 600 transistors. The demo processor, called Analog Calculation Unit (ACU), is designed and simulated in a standard CMOS technology for proof-of-concept. From the circuit simulation results, the proposed ACU calculates all the target functions in real-time with the error less than 4.3 %. The performances over speed, functions, and hardware efficiency of proposed ACU are superior to a basic four-bit digital Arithmetic Logic Unit (ALU). Obviously, the calculation ability of presented ACU is higher than the simple four-bit ALU which processes only several basic arithmetic and logic functions. The number of transistors of the ACU is only 4.9 % of the minimum estimation of conventional field programmable gate array (FPGA) for arbitrary four-bit calculations. In addition, the static power of the designed ACU is eliminated by using our proposed power-gating scheme.