SEE in a 0.15 /spl mu/m fully depleted CMOS/SOI commercial Process
SEE in a 0.15 /spl mu/m fully depleted CMOS/SOI commercial Process
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0.15 /spl mu/m 完全耗尽 CMOS/SOI 商业工艺中的 SEE
DOI:
10.1109/tns.2004.839155
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发表时间:
2004
影响因子:
1.8
通讯作者:
S. Matsuda
中科院分区:
文献类型:
--
作者:
A. Makihara;T. Yamaguchi;Y. Tsuchiya;T. Arimitsu;H. Asai;Y. Iide;H. Shindou;S. Kuboyama;S. Matsuda
We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.