CACI: Dynamic current analysis towards robust recycled chip identification
CACI: Dynamic current analysis towards robust recycled chip identification
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CACI：动态电流分析以实现稳健的回收芯片识别
DOI：
10.1145/2593069.2593102
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
S. Bhunia
中科院分区：
文献类型：
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作者：
Yu Zheng;A. Basak;S. Bhunia
供应链中假冒筹码的发生率上升对半导体行业构成了严重威胁。二手芯片的回收构成了伪造攻击的一种主要形式。如果未被发现，它们可能会导致严重的后果，包括在现场运营期间的系统性能/可靠性问题以及值得信赖的制造商的潜在收入/声誉损失。基于路径延迟分析的现有验证方法在较大的过程变化下的鲁棒性和灵敏度降低。另一方面，基于老化传感器的现有设计解决方案需要额外的设计/验证工作，并且不能应用于传统芯片。在本文中，我们提出了一种新型的回收芯片识别方法CACI，该方法利用了自相似模块（例如，加法器的不同部分）中的差异老化，以在较大的间和内部过程变化下分离老化的芯片。它比较了芯片中两个相邻的相似电路结构之间的动态电流（IDDT）签名。我们根据多个电流比较得出一个隔离度量，以提供高水平的置信度。 CACI不依靠任何嵌入式结构进行身份验证，因此它实际上是零设计开销，可以应用于已经在市场上的芯片。通过广泛的模拟，我们表明，对于45nm CMOS工艺，阈值电压内部和10％的内部变化，可以可靠地识别出超过97％的再生芯片。
Rising incidences of counterfeit chips in the supply chain have posed a serious threat to the semiconductor industry. Recycling of used chips constitutes a major form of counterfeiting attacks. If undetected, they can lead to serious consequences including system performance/reliability issues during field operation and potential revenue/reputation loss for a trusted manufacturer. Existing validation approaches based on path delay analysis suffer from reduced robustness and sensitivity under large process variations. On the other hand, existing design solutions based on aging sensors require additional design/verification efforts and cannot be applied to legacy chips. In this paper, we present a novel recycled chip identification approach, CACI, that exploits differential aging in self-similar modules (e.g., different parts of an adder) to isolate aged chips under large inter- and intra-die process variations. It compares dynamic current (IDDT) signatures between two adjacent similar circuit structures in a chip. We derive an isolation metric based on multiple current comparisons to provide high level of confidence. CACI does not rely on any embedded structures for authentication, thus it comes at virtually zero design overhead and can be applied to chips already in the market. Through extensive simulations, we show that for 15% inter- and 10% intra-die variations in threshold voltage for a 45nm CMOS process, over 97% of recycled chips can be reliably identified.