Standby power reduction using dynamic voltage scaling and canary flip-flop structures
Standby power reduction using dynamic voltage scaling and canary flip-flop structures
复制标题
使用动态电压调节和金丝雀触发器结构降低待机功耗
DOI：
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发表时间：
2004
影响因子：
5.4
通讯作者：
A. Chandrakasan
中科院分区：
文献类型：
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作者：
B. Calhoun;A. Chandrakasan
在待机模式期间降低V/sub DD/可通过降低电压和电流来降低功耗。对触发器结构的分析表明，在破坏状态信息之前，电压可以缩放到多低。对0.13-/spl mu/m、双V/sub T/测试芯片的测量表明，将V/sub DD/降低到接近状态丢失的点可以获得最佳的功率节省。我们发现，“金丝雀”触发器提供了一种机制，观察接近失败的触发器。金丝雀触发器实现闭环待机电压缩放，以实现接近最佳的节能效果。这种方法潜在地提供了比没有状态丢失的最佳开环方法高2/spl倍的节省。
Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-/spl mu/m, dual-V/sub T/ test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2/spl times/ higher savings than an optimal open-loop approach without loss of state.