Design of a Compact Modular Exponentiation Accelerator for Modern FPGA Devices
Design of a Compact Modular Exponentiation Accelerator for Modern FPGA Devices
复制标题
现代 FPGA 器件的紧凑型模块化幂加速器设计
DOI：
10.1016/j.compeleceng.2007.05.007
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
T. Hämäläinen
中科院分区：
文献类型：
--
作者：
T. Alho;Panu Hämäläinen;Marko Hännikäinen;T. Hämäläinen
我们提出了一个紧凑的FPGA实现的模幂运算加速器适合于密码应用。该实现有效地利用了现代FPGA的特性。该加速器消耗434个逻辑元件，4个9位DSP元件，以及Altera Stratix EP1S40中的13604个存储器位。它可以执行最多2250位整数的模幂运算，并可以轻松扩展到更大的幂运算。不包括预处理和后处理时间，1024位和2048位求幂分别在26.39ms和199.11ms内执行。由于其紧凑性、标准接口和对不同时钟域的支持，该加速器可以毫不费力地集成到同一FPGA中的更大系统中。该加速器和它的性能在实践中证明了一个完整的功能的原型实现，包括软件和硬件组件。
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of modern FPGAs. The accelerator consumes 434 logic elements, four 9-bit DSP elements, and 13604 memory bits in Altera Stratix EP1S40. It performs modular exponentiations with up to 2250-bit integers and scales easily to larger exponentiations. Excluding pre- and post-processing time, 1024-bit and 2048-bit exponentiations are performed in 26.39ms and 199.11ms, respectively. Due to its compactness, standard interface, and support for different clock domains, the accelerator can effortlessly be integrated into a larger system in the same FPGA. The accelerator and its performance are demonstrated in practice with a fully functional prototype implementation consisting of software and hardware components.