Memristor based programmable threshold logic array
Memristor based programmable threshold logic array
复制标题
基于忆阻器的可编程阈值逻辑阵列
DOI：
--
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
G. Rose
中科院分区：
文献类型：
--
作者：
Jeyavijayan Rajendran;H. Manem;R. Karri;G. Rose
在这项工作中，我们利用忆阻器实现功率和面积有效的可编程阈值门。忆阻器被用作阈值门的输入处的权重。通过改变忆阻来编程阈值门，以实现不同的布尔函数。提出了一种新的阈值门阵列结构，并对功耗、面积和延迟指标进行了评估。用于评估上述架构的CAD设置也可用于分析新兴计算技术的性能。所提出的架构实现了75%的平均功耗降低和面积（晶体管数）减少75%相比，查找表（LUT）为基础的逻辑与一些延迟惩罚。
In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.