Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
复制标题
基于施密特触发器的超低压工艺变化容错 SRAM 设计
DOI：
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发表时间：
2012
影响因子：
2.8
通讯作者：
K. Roy
中科院分区：
文献类型：
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作者：
J. Kulkarni;K. Roy
我们分析了Schmitt-Trigger（ST）基于差异的静态随机访问存储器（SRAM），用于超级电压操作与标准的6T比特小组相比，ST操作提供了更好的阅读稳定性和更好的写入。实现过程差异 - 未来的纳米级技术节点必须在ISO-AREA条件下进行详细的比较。 -NM CMOS技术表明，与较高的ST-2 Bitcell相比ISO-AREA 6T BITCELL。
We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.