Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
复制标题
使用 RISC-V 生态系统在 TSMC 16nm 中设计以加速器为中心的 SoC 的经验
DOI：
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发表时间：
2017
期刊：
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通讯作者：
Zhiru Zhang
中科院分区：
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作者：
T. Ajayi;Khalid Al;Aporva Amarnath;Steve Dai;S. Davidson;Paul Gao;Gai Liu;Anuj Rao;A. Rovinski;Ning;Christopher Torng;Luis Vega;Bandhav Veluri;Shaolin Xie;Chun Zhao;Ritchie Zhao;C. Batten;R. Dreslinski;Rajesh K. Gupta;M. Taylor;Zhiru Zhang
不幸的是，不幸的是，以自定义的芯片在原型系统中展示新的研究思想的最新趋势是重新构建了这种研究原型。部分通过减少设计，实施和验证工作来应对这一挑战。嵌入式应用的性能和能源效率包括五个RV64G核心，496核RV32IM瓷砖多核处理器和一个复杂的BNN（双核神经网络）加速器描述我们使用RISC-V生态系统来建立腹部的经验，并突出了利用RISC-V指令集，RISC-V软件堆栈，RISC-V处理器和内存系统生成器，RISC-RISC-V-v in-CHIP网络接口，RISC-V验证套件和RISC-V系统级硬件基础架构
The recent trend towards accelerator-centric architectures has re-newed the need for demonstrating new research ideas in prototype systems with custom chips. Unfortunately, building such research prototypes is tremendously challenging, but the emerging RISC-V open-source software and hardware ecosystem can partly address this challenge by reducing design, implementation, and verification effort. This paper briefly describes the Celerity system-on-chip (SoC), a 5 × 5mm 385M-transistor chip in TSMC 16nm, which uses a tiered parallel accelerator fabric to improve both the performance and energy efficiency of embedded applications. The Celerity SoC includes five RV64G cores, a 496-core RV32IM tiled manycore processor, and a complex BNN (binarized neural network) accelerator implemented as a Rocket custom co-processor (RoCC). We describe our experiences using the RISC-V ecosystem to build Celerity, and highlight both key benefits and challenges in leveraging the RISC-V instruction set, RISC-V software stack, RISC-V processor and memory system generators, RISC-V on-chip network interfaces, RISC-V verification suite, and RISC-V system-level hardware infrastructure. The RISC-V ecosystem