Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
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DOI：
10.1145/344166.344526
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发表时间：
2000-08
期刊：
影响因子：
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通讯作者：
Michael D. Powell;Se-Hyun Yang;B. Falsafi;K. Roy;T. N. Vijaykumar
中科院分区：
文献类型：
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作者：
Michael D. Powell;Se-Hyun Yang;B. Falsafi;K. Roy;T. N. Vijaykumar
深亚微米的CMOS设计导致微处理器的漏电能量消耗很大。虽然片上高速缓冲存储器中的SRAM单元总是导致这种泄漏，但在应用内和应用之间，活动单元的使用都有很大的变异性。本文探索了一种集成的体系结构和电路级方法，以减少指令高速缓存中的泄漏能量消耗。我们提出了门控Vdd，这是一种电路级技术，用于选通电源电压并减少未使用的SRAM单元中的泄漏。我们的结果表明，门控Vdd与一种新颖的可调整大小的缓存结构相结合，在对性能影响最小的情况下，将能量延迟降低了62%。
Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appliðcations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instrucðtion caches. We propose, gated-Vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-Vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.