Shakti-T: A RISC-V Processor with Light Weight Security Extensions
Shakti-T: A RISC-V Processor with Light Weight Security Extensions
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Shakti-T：具有轻量级安全扩展的 RISC-V 处理器
DOI：
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发表时间：
2017
期刊：
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通讯作者：
Kamakoti Veezhinathan
中科院分区：
文献类型：
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作者：
Arjun Menon;S. Murugan;C. Rebeiro;Neel Gala;Kamakoti Veezhinathan
随着敏感应用（包括电子商务）对计算核心的使用增加，需要提供额外的硬件支持以保护信息免受基于存储器的攻击。这项工作提出了一个统一的硬件框架，用于处理空间和时间的内存攻击。本文将所提出的硬件框架与基于RISC-V的微架构集成在一起，该微架构具有增强的应用程序二进制接口，使软件层能够使用这些功能来保护敏感数据。我们证明了所提出的方案的有效性，通过实际的案例研究，除了通过超大规模集成电路CAD设计流程的设计。与现有解决方案相比，所提出的处理器将元数据存储开销降低了4倍，同时在FPGA上产生的面积开销仅为1914个LUT和2197个触发器，而不会影响处理器的关键路径延迟。
With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor.