First-Order Recursive CIC Filters in Time-Interleaved VCO-Based ADCs for Direct-RF Sampling Receivers
First-Order Recursive CIC Filters in Time-Interleaved VCO-Based ADCs for Direct-RF Sampling Receivers
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DOI：
10.1109/apccas47518.2019.8953087
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发表时间：
2019-11
期刊：
影响因子：
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通讯作者：
Yuma Isobe;T. Kihara
中科院分区：
文献类型：
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作者：
Yuma Isobe;T. Kihara
在直接射频（RF）采样接收器中以每秒千兆采样（GS/s）速率操作的数字构建块消耗接收器的大量总功率。以前报道的技术没有考虑模数转换器（ADC）中的数字模块，也没有降低功耗。我们首先将抽取因子为2的一阶递归级联积分梳状（CIC）滤波器放置在时间交错ADC（TI-ADC）之后，TI-ADC由压控振荡器（VCO）、采样器、鉴相器和微分器组成。该CIC滤波器利用积分器抵消微分器，并将采样器的时钟频率减半，以降低接收机的功耗。我们采用65 nm CMOS工艺设计了一个直接RF采样接收机的数字模块，该接收机采用3.6 GS/s 4通道TI VCO ADC，适用于Sub-GHz应用（鉴相器、混频器和CIC滤波器）。仿真结果表明，布局布线电路工作在450-MS/s的速率与3.6 mW，这是没有提出的方法的数字电路的功耗的一半。
Digital building blocks operating at gigasamples per second (GS/s) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analog-to-digital converters (ADCs) and not decreased the power consumption. We first place first-order recursive cascaded integrator-comb (CIC) filters with decimation factors of two after time-interleaved ADCs (TI-ADCs), consisting of voltage-controlled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a direct-RF sampling receiver with a 3.6-GS/s 4-channel TI VCO-based ADC for Sub-GHz applications (phase detectors, mixers, and CIC filters) by using a 65-nm CMOS process. Simulations show that the place-and-routed circuit operates at a 450-MS/s rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.