Analysis of surface state effect on gate lag phenomena in GaAs MESFET's
Analysis of surface state effect on gate lag phenomena in GaAs MESFET's
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GaAs MESFET 栅极滞后现象的表面态效应分析
DOI：
10.1109/16.310100
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发表时间：
1994
影响因子：
3.1
通讯作者：
Chien
中科院分区：
文献类型：
--
作者：
S. Lo;Chien
本文对GaAsMESFET栅滞后现象进行了二维瞬态模拟。我们的研究结果表明，电荷交换的人口的表面态在FET的非门接入区负责这种缓慢的瞬态现象。所测量的“空穴陷阱样”DLTS信号与在填充脉冲期间捕获的空穴的再发射直接相关。较高的选通脉冲对表面电荷密度的调制作用较大，会导致更严重的滞后现象。具有较短N/sup +/-栅间距和较低表面态密度的器件具有较小的栅滞后效应。>
A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured "hole-trap-like" DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N/sup +/-gate spacing and lower surface state densities are shown to have less gate lag effect. >