SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC
SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC
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DOI：
10.1142/s021812661350028x
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发表时间：
2013-04-01
影响因子：
1.5
通讯作者：
Toms, W. B.
中科院分区：
文献类型：
--
作者：
Balasubramanian, P.;Edwards, D. A.;Toms, W. B.
本文对自定时计算机算法领域作出了两个重要贡献。首先，讨论了基于分段进位概念的自定时超前进位加法器的门级综合。三种类型的CLA加法器的架构已被认为是同质和异构延迟不敏感（DI）的数据编码方案。一般来说，对于高阶加法，自定时CLA加法器的延迟比进位涟漪版本减少了38.6%。然而，后者所占面积较小，功耗较前者分别低37.8%和17.4%。其次，在这项工作中引入了一个新的概念，混叠逻辑是有用的延迟优化的迭代电路规格-在这里，这个概念被施加到自定时CLA加法器的延迟减少。通过结合混叠逻辑，CLA结构中的中间载波的传播延迟被进一步最小化到平均27.2%的调谐，同时伴随着分别仅2%和1.5%的数量级的边际面积和功率损失。
This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications - here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.