Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing
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用于基于 FPGA 的图像处理的加速和节能的内存访问优化
DOI：
10.1109/isocc56007.2022.10031293
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发表时间：
2022
期刊：
影响因子：
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通讯作者：
Keiji Kishine
中科院分区：
文献类型：
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作者：
Shungo Shimohane;Toshiyuki Inoue;Akira Tsuchiya;Keiji Kishine
在本文中，我们提出了一种基于FPGA的图像处理的加速和节能的方法，通过优化存储器访问。基于BRAM的系统通过将图像处理后的数据存储在BRAM中，提高了FPGA与存储器之间的数据传输速度。此外，它不需要额外的驱动程序来吸收延迟，这导致减少硬件资源的使用和功耗。我们的存储器访问优化，使处理速度提高了约9倍，功耗降低了10%，相比传统的DRAM为基础的系统。
In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.