Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection
复制标题
使用测试时电压选择集成动态电压/频率缩放和自适应体偏置
DOI：
10.1145/1594233.1594284
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
L. Pileggi
中科院分区：
文献类型：
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作者：
A. Bonnoit;S. Herbert;Diana Marculescu;L. Pileggi
自适应体偏置是一种很有前途的技术，用于解决日益增加的工艺可变性，但它也提供了新的机会，降低功耗时，结合动态电压/频率缩放。现有的ABB/DVFS建议的局限性进行了探讨，并提出了一种新的方案，测试时间电压选择（TTVS）。通过延迟频率和电源电压之间的映射直到测试，可变性信息可以被并入VDD选择过程。对于采用高性能预测22 nm技术实现的16核芯片多处理器，TTVS比独立ABB/DVFS节省18%的功耗，比先前提出的几种ABB/DVFS方案节省11%的功耗。
Adaptive body biasing is a promising technique for addressing increasing process variability, but it also provides new opportunities for reducing power when combined with dynamic voltage/frequency scaling. Limitations of existing ABB/DVFS proposals are explored, and a new scheme, test-time voltage selection (TTVS), is presented. By delaying the mapping between frequency and supply voltage until test, variability information can be incorporated into the VDD selection process. For a 16-core chip-multiprocessor implemented in a high-performance predictive 22 nm technology, TTVS results in 18% power savings over independent ABB/DVFS and 11% power savings over the best of several previously proposed ABB/DVFS schemes.