Processor caches built using multi-level spin-transfer torque RAM cells
Processor caches built using multi-level spin-transfer torque RAM cells
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DOI：
10.1109/islped.2011.5993610
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发表时间：
2011-08
期刊：
影响因子：
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通讯作者：
Yiran Chen;W. Wong;Hai Helen Li;Cheng-Kok Koh
中科院分区：
文献类型：
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作者：
Yiran Chen;W. Wong;Hai Helen Li;Cheng-Kok Koh
据预测，从目前开始，处理器的缓存将占据技术节点芯片面积的90%。在本文中，我们研究了多级自旋传递扭矩RAM （STT-RAM）单元在处理器缓存设计中的应用。与传统的SRAM缓存相比，多层单元（MLC） STT-RAM缓存设计更密集，速度更快，能耗更低。然而，在MLC STT-RAM技术应用于处理器缓存之前，仍有许多关键问题有待解决。在本文中，我们将提供位编码问题的解决方案以及解决写入持久性问题。后者在之前关于STT-RAM缓存的工作中被忽略了。我们提出了一种集重映射方案，可以将MLC STT-RAM缓存的寿命平均延长80倍。此外，还介绍了一种恢复在某些应用程序中由于集合重新映射而可能丢失的性能的方法。
It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a multi-level cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of critical issues remains to be solved before MLC STT-RAM technology can be deployed in processor caches. In this paper, we shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. The latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80× on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is introduced.