Breaking the simulation barrier: SRAM evaluation through norm minimization
Breaking the simulation barrier: SRAM evaluation through norm minimization
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DOI：
10.1109/iccad.2008.4681593
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发表时间：
2008-11
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影响因子：
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通讯作者：
L. Dolecek;Masood Qazi;Devavrat Shah;A. Chandrakasan
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文献类型：
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作者：
L. Dolecek;Masood Qazi;Devavrat Shah;A. Chandrakasan
随着工艺变化成为深亚微米技术中日益关注的问题，有效地获得SRAM元件失效概率的准确估计的能力正成为一个中心问题。在本文中，我们提出了一种快速、准确地评估存储器设计失效概率的通用方法。所提出的统计方法，我们称之为通过范数最小化原理的重要性抽样，减少了估计量的方差，以产生快速估计。它建立在重要性抽样的基础上，同时使用了一种新的范数最小化原理，该原理受到经典大偏差理论的启发。我们的方法可以适用于广泛的一类问题，我们的说明性例子是32 nm工艺的6T SRAM的数据保持电压和读/写失败权衡。在本文所考虑的静态随机存储器失效概率估计中，该方法比标准的蒙特卡罗方法节省了约10000倍的计算。
With process variation becoming a growing concern in deep submicron technologies, the ability to efficiently obtain an accurate estimate of failure probability of SRAM components is becoming a central issue. In this paper we present a general methodology for a fast and accurate evaluation of the failure probability of memory designs. The proposed statistical method, which we call importance sampling through norm minimization principle, reduces the variance of the estimator to produce quick estimates. It builds upon the importance sampling, while using a novel norm minimization principle inspired by the classical theory of Large Deviations. Our method can be applied for a wide class of problems, and our illustrative examples are the data retention voltage and the read/write failure tradeoff for 6T SRAM in 32 nm technology. The method yields computational savings on the order of 10000x over the standard Monte Carlo approach in the context of failure probability estimation for SRAM considered in this paper.