A Design Method of Phase-Locked Loop for Grid-Connected Converters Considering the Influence of Current Loops in Weak Grid
A Design Method of Phase-Locked Loop for Grid-Connected Converters Considering the Influence of Current Loops in Weak Grid
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DOI：
10.1109/jestpe.2019.2916002
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发表时间：
2020-09
影响因子：
5.5
通讯作者：
Xing Li;Hua Lin
中科院分区：
文献类型：
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作者：
Xing Li;Hua Lin
在弱电网条件下，锁相环（PLL）带宽不合理会导致并网电压源变换器（VSCs）潜在的不稳定问题。随着碳化硅（SiC）和氮化镓（GaN）半导体材料的发展，VSCs的电流回路可以更快地设计。锁相环的带宽是否也可以设计得更高，以适应更快的电流环，这是值得怀疑的。因此，首先研究电流环的带宽与锁相环带宽的关系。结果表明，锁相环的带宽可能不会随着电流环带宽的增加而线性增加，因此，传统的锁相环带宽不高于电流环带宽的十分之一的设计原则可能不再适用。因此，本文提出了一种锁相环的设计方法，使并网VSCs在弱电网条件下具有足够的稳定裕度和满意的动态性能。电流环是独立设计的，而锁相环的设计考虑了弱电网条件下电流环与锁相环的耦合。仿真和实验结果验证了理论分析和提出的设计方法。
Phase-locked loop (PLL) with improper bandwidth could lead to potential instability issues for the grid-connected voltage-source converters (VSCs) under weak grid conditions. The current loops of the VSCs can be designed faster as the development of the silicon carbide (SiC) and gallium nitride (GaN) semiconductor materials. It is questionable whether the PLL’s bandwidth could also be designed higher for faster current loop. Hence, the relationship between the bandwidth of the current loop and the bandwidth of the PLL is studied first. It is revealed that the bandwidth of the PLL might not be increased linearly with the increasing of the bandwidth of the current loop, and thus, the traditional design principle, i.e., the bandwidth of the PLL is not higher than one-tenth of that of the current loop, might no longer be suitable. Thus, this paper proposes a design method of the PLL to make the grid-connected VSCs to have adequate stability margin and satisfactory dynamic performances under weak grid conditions. The current loop is designed independently, while the PLL is designed considering the coupling between the current loop and the PLL under weak grid conditions. The simulations and experimental results verify the theoretical analysis and the proposed design method.