An Analysis of Instruction-Fetching Strategies in Pipelined Computers
An Analysis of Instruction-Fetching Strategies in Pipelined Computers
复制标题
流水线计算机取指令策略分析
DOI：
--
复制
发表时间：
1980
影响因子：
3.7
通讯作者：
R. Ibbett
中科院分区：
文献类型：
--
作者：
R. Holgate;R. Ibbett
流水线处理器的性能受控制转移或分支指令的影响很大，各种策略已被用来减少由这些指令引起的延迟。然而，“控制点”在管道中的位置是一个必须考虑的重要因素，本文对其影响进行了分析。给出了在高度流水线的MU5处理器上运行基准程序期间使用硬件性能监视器进行的测量结果。这些结果支持将控制点放置在流水线中越晚越好，并且使用预测机制向流水线提供正确的指令序列的论点。
The performance of pipelined processors is heavily influenced by the effects of control-transfer, or branching, instructions, and various strategies have been used to reduce the delays incurred by these instructions. The position of the "control point" in the pipeline is an important factor that must also be taken into account, however, and this paper presents an analysis of its effects. Results are given of measurements made with a hardware performance monitor during the running of benchmark programs on the highly pipelined MU5 processor. These results support the argument for placing the control point as late in the pipeline as possible, and for using a prediction mechanism to supply correct sequences of instructions to the pipeline.