Thermal aware modern VLSI floorplanning
Thermal aware modern VLSI floorplanning
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DOI：
10.1109/icdcsyst.2012.6188701
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发表时间：
2012-03
期刊：
影响因子：
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通讯作者：
Nirmala Rani D. Gracia;Srinath Rajaram;N. Nivethitha;A. Sudarsan
中科院分区：
文献类型：
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作者：
Nirmala Rani D. Gracia;Srinath Rajaram;N. Nivethitha;A. Sudarsan
在这项工作中，我们提出了一个基于遗传（GA）算法的热感知地板规划框架。地板规划的主要目标是将容纳芯片上所有功能块所需的总面积最小化，同时降低高温，并在框架内的芯片上均匀分布温度。采用遗传（GA）算法的B*树表示来计算基于功耗的地板规划温度。利用热点工具降低高温，利用算法去除死区。面积和/或温度优化引导GA算法生成最终的最适解。使用MCNC基准测试的实验结果表明，我们的组合面积和热优化技术充分降低了峰值温度，同时提供了与传统面向面积的技术一样紧凑的平面图。
In this work, we present a Genetic (GA) algorithm based thermal-aware floorplanning framework. The primary objective for floorplanning is to minimize the total area required to accommodate all of the functional blocks on a chip and also to reduce high temperature and to distribute temperature evenly across a chip in an framework. B*tree representations with Genetic (GA) algorithm is used to calculate floorplanning temperature based on the power dissipation. The hotspot tool is used to reduce the high temperature and the algorithm is used to remove the dead space area. Area and/or temperature optimizations guide the GA algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.