Compact lumped element model for TSV in 3D-ICs
Compact lumped element model for TSV in 3D-ICs
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DOI：
10.1109/iscas.2011.5938067
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发表时间：
2011-05
期刊：
影响因子：
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通讯作者：
K. Salah;A. El-Rouby;H. Ragai;K. Amin;Y. Ismail
中科院分区：
文献类型：
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作者：
K. Salah;A. El-Rouby;H. Ragai;K. Amin;Y. Ismail
提出了一种基于电磁仿真的硅通孔宽带集总元件模型。介绍了基于量纲分析法的TSV寄生效应的封闭表达式。所提出的模型，使直接提取的TSV电阻，自感，氧化物电容，和寄生元素，由于有限的衬底电阻率。该模型的紧凑性和兼容性与SPICE模拟允许快速调查的TSV对3-D电路性能的影响。所提出的TSV模型的参数值与模拟的S参数在10 GHz以下拟合，误差小于5%。它示出的TSV电容是高度依赖于接地触点的位置，并在一个典型的电流技术中具有数十毫微微法拉的值。该值远高于最小器件电容，需要特殊的设计方法，如级联缓冲器。TSV之间的耦合将在另一篇论文中处理。
A wide-band lumped element model for a through silicon via (TSV) is proposed based on electromagnetic simulations. Closed form expressions for the TSV parasitics based on the dimensional analysis method are introduced. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed TSV model are fitted to the simulated S-parameters up to 10 GHz with an error less than 5%. It is shown that a TSV capacitance is highly dependent on the positions of ground contacts and has a value of tens of femto farads in a typical current technology. This value is much higher than a minimum device capacitance and requires special design methodologies such as cascaded buffers. Coupling between TSVs will be handled in another paper.