Logic Design of Programmable Logic Arrays
Logic Design of Programmable Logic Arrays
复制标题
可编程逻辑阵列的逻辑设计
DOI：
10.1109/tc.1979.1675428
复制
发表时间：
1979
影响因子：
3.7
通讯作者：
Y. Kambayashi
中科院分区：
文献类型：
--
作者：
Y. Kambayashi
与随机逻辑电路相比，存储器型电路更适合LSI实现，因为其相同单元的迭代结构导致更高的晶体管密度和更高的成品率。可编程逻辑阵列（PLA）是一种具有可编程地址的只读存储器（ROM），适合于实现具有多种未指定输入组合的逻辑功能。对于这样的功能，在许多情况下可以减少输入数量。由于PLA的成本主要由引脚数量和芯片决定，两者都受到输入数量的影响，因此减少输入数量在PLA设计中非常重要。另一方面，减少乘积和表达式中的乘积项的数量在传统的随机逻辑综合中很重要。由于输入数量和乘积项数量之间存在权衡问题，因此我们按照以下优先顺序给出设计过程：1）最小化引脚数量，2）最小化乘积项数量，3）最小化PLA中使用的电路数量。这些因素也决定了芯片所需的面积。
Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield. A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations. For such a function, reduction of the number of input is possible in many cases. Since the cost of a PLA is mainly determined by the number of pins and the chip, both of which are affected by the number of inputs, the reduction of the number of inputs is very important in PLA design. On the other hand, the reduction of the number of product terms in a sum-of-product expression is important in conventional random logic synthesis. Since there is a tradeoff problem between the number of inputs and the number of product terms, we give a design procedure by the following preference order: 1) minimizing the number of pins, 2) minimizing the number of product terms, 3) minimizing the number of circuits used in the PLA. These factors also determine the area required for a chip.