Advanced system on a chip design based on controllable-polarity FETs
Advanced system on a chip design based on controllable-polarity FETs
复制标题
基于可控极性 FET 的先进片上系统设计
DOI：
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发表时间：
2014
期刊：
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通讯作者：
G. Micheli
中科院分区：
文献类型：
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作者：
P. Gaillardon;L. Amarù;Jian Zhang;G. Micheli
具有在线可换极性的场效应晶体管（FET）是支持下一代系统芯片（SoC）的有希望的候选者。由于其增强的功能，可换极性FET能够实现SoC中关键组件（如处理单元和存储器）的上级设计，同时还提供控制功耗的本地解决方案。在本文中，我们提出了一个有效的设计SoC核心与双极性FET。处理单元在数据路径级加速，因为算术运算需要比标准CMOS更少的物理资源。通过嵌入式功率门控技术和可调高性能/低功耗器件操作降低了功耗。通过将存取接口与存储电路合并，存储器单元变得更小。我们预见到这些技术带来的优势，通过评估其对SoC设计的影响，为当代电信应用。使用22纳米垂直堆叠的硅纳米线技术，在块级的粗粒度评估估计延迟和功耗分别降低20%和19%，在一个中等的面积开销为15%的成本，相对于一个国家的最先进的FinFET技术。
Field-Effect Transistors (FETs) with on-line controllable-polarity are promising candidates to support next generation System-on-Chip (SoC). Thanks to their enhanced functionality, controllable-polarity FETs enable a superior design of critical components in a SoC, such as processing units and memories, while also providing native solutions to control power consumption. In this paper, we present the efficient design of a SoC core with controllable-polarity FET. Processing units are speeded-up at the datapath level, as arithmetic operations require fewer physical resources than in standard CMOS. Power consumption is decreased via embedded power-gating techniques and tunable high-performance/low-power devices operation. Memory cells are made smaller by merging the access interface with the storage circuitry. We foresee the advantages deriving from these techniques, by evaluating their impact on the design of SoC for a contemporary telecommunication application. Using a 22-nm vertically-stacked silicon nanowire technology, a coarse-grain evaluation at the block level estimates a delay and power reduction of 20% and 19% respectively, at a cost of a moderate area overhead of 15%, with respect to a state-of-art FinFET technology.