Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning
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DOI：
10.1109/aspdac.2018.8297285
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发表时间：
2018-01
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影响因子：
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通讯作者：
H. Sayadi;Divya Pathak;I. Savidis;H. Homayoun
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文献类型：
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作者：
H. Sayadi;Divya Pathak;I. Savidis;H. Homayoun
异类多核处理器(HMP)由多种核心类型(小型核心架构与大型核心架构)组成，具有不同的性能和电源特性，可灵活地将每个线程分配到可提供最高能效的核心。尽管这种体系结构为运行的应用程序提供了更大的灵活性来确定最大能效的最佳运行时设置，但由于各种调整参数(如内核类型、运行时电压和频率以及线程数量)的相互依赖，调度变得更具挑战性。更重要的是，片上电压调节器(OCVR)的功率转换效率(PCE)的影响是另一个重要参数，这使得在HMP上调度多线程应用程序变得更具挑战性。本文讨论了电路和结构参数的并行优化和微调对HMPs节能调度的重要性，以利用异构性的力量。此外，针对考虑功率转换效率影响的HMP体系结构，研究了多线程应用程序的调度挑战。为了指导调度决策，开发了一个高精度的基于学习的能效预测模型。利用预测模型，我们进一步开发了一种PCE感知调度方案，用于将多线程应用程序有效地映射到HMP上。结果表明，在大核和小核之间没有PCE差距的情况下，所提出的基于学习的方法比现有的方法提高了10%。当大核和小核之间的PCE差距增大时，能效提高高达60%。
Heterogeneous Multicore Processors (HMPs) are comprised of multiple core types (small vs. big core architectures) with various performance and power characteristics which offer the flexibility to assign each thread to a core that provides the maximum energy-efficiency. Although this architecture provides more flexibility for the running application to determine the optimal run-time settings that maximize energy-efficiency, due to the interdependence of various tuning parameters such as the type of core, run-time voltage and frequency, and the number of threads, the scheduling becomes more challenging. More importantly, the impact of Power Conversion Efficiency (PCE) of the On-Chip Voltage Regulators (OCVRs) is another important parameter that makes it more challenging to schedule multithreaded applications on HMPs. In this paper, the importance of concurrent optimization and fine-tuning of the circuit and architectural parameters for energy-efficient scheduling on HMPs is addressed to harness the power of heterogeneity. In addition, the scheduling challenges for multithreaded applications are investigated for HMP architectures that account for the impact of power conversion efficiency. A highly accurate learning-based model is developed for energy-efficiency prediction to guide the scheduling decision. Using the predictive model, we further develop a PCE-aware scheduling scheme is developed for effective mapping of multithreaded applications onto an HMP. The results indicate that the proposed learning-based scheme outperforms the state of the art solution by 10% when there is no PCE gap between big and little cores. The energy-efficiency improves up to 60% when the PCE gap between big and little cores increases.